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Silicon Labs /Series1 /EFM32GG12B /EFM32GG12B810F1024GM64 /USB /HCFG

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Interpret as HCFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FSLSPCLKSEL 0 (FSLSSUPP)FSLSSUPP 0 (ENA32KHZS)ENA32KHZS 0RESVALID0 (MODECHTIMEN)MODECHTIMEN

Description

Host Configuration Register

Fields

FSLSPCLKSEL

FS/LS PHY Clock Select

1 (DIV1): Internal PHY clock is running at 48 MHz (undivided).

2 (DIV8): Internal PHY clock is running at 6 MHz (48 MHz divided by 8).
FSLSSUPP

FS- and LS-Only Support
ENA32KHZS

Enable 32 kHz Suspend Mode
RESVALID

Resume Validation Period
MODECHTIMEN

Mode Change Time

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data